Alignment marks and aligning wafers with respect to those marks are an important part of the process of manufacturing semiconductor devices and integrated circuits. Integrated circuits are manufactured by patterning a sequence of masking layers and the features on successive layers bear a spatial relationship to one another. As part of the manufacturing process each level must be aligned to the previous levels. Alignment of one pattern layer to previous layers is done with the assistance of special alignment patterns designed onto each mask level. When these special patterns are aligned, it is assumed that the remainder of the integrated circuit patterns are also correctly aligned. Since each layer must have alignment marks for proper registration with respect to the next layer, each alignment or registration then becomes layer dependent.
The tools that are used to pattern the various layers in a wafer are known as photomask or mask and reticles. The patterns on the mask or the reticle are defined by a combination of opaque and translucent areas. A light source shone through the mask or the reticle projects the pattern onto the surface of a semiconductor wafer, and depending upon the material that has been exposed to the light, the pattern is transferred onto the surface where the light arrives or where no light is shone on a semiconductor wafer surface. A mask contains patterns that can be transferred to an entire wafer in one exposure. A reticle, on the other hand, contains a pattern image that must be stepped and repeated in order to expose the entire semiconductor substrate surface.
The adjustments of the image of the mask being exposed to the previously produced patterns was originally performed by human operators, who compared the image locations under a microscope and adjusted the position of the mask to bring it into alignment with the wafer patterns. The decrease in feature sizes, and the increase in the number of alignments per wafer with step-and-repeat projector aligners, has been the impetus for developing automatic alignment systems.
Again, patterning is one of the basic steps used in performing semiconductor processing. It is also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate or wafer (or removal of portions of the wafer), as a result of a deposition process. For example, as shown in FIG. 1A, a layer 104 has been deposited on a substrate 102. After the photolithography process is performed, as shown in FIG. 1B, some parts of layer 104 had been selectively removed, such that gaps 106a and 106b are present within the layer 104. A photomask, or pattern, is used (as shown in FIG. 1B) so that only the material from the gaps 106a and 106b are removed, and not the other portions of the layer 104. The process of adding layers and removing selected parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Again, alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, and may be discarded as scrap. Such misalignment, or overlay shift, is shown in FIG. 2. The layer 204 may or may not be deposited in a properly aligned configuration on substrate 202, whereas subsequent deposition layers 206a, 206b, . . . , 206n are misaligned. This is indicated by the reference marks 210a, 210b, . . . , 210n, which are shown in FIG. 2 for illustrative clarity only. The reference marks 210a, 210b, . . . , 210n, should substantially align over the alignment marks 208 of the substrate 202, however, in this case the marks do not.
In comparison to FIG. 2, correctly aligned layers are shown in FIG. 3. The semiconductor wafer 202 has alignment marks 208. A layer 204 is aligned thereupon. Similarly the layers 206a, 206b, . . . , 206n are deposited upon the layer 204, without any, or with minimal, overlay shift. This is indicated by the reference marks 210a, 210b, 210n aligning with the alignment marks 208 of the wafer 202.
Specific type of alignment problems can result when using epitaxial layers grown over a semiconductor substrate. Epitaxy is the process in which a thin layer of a single crystal material is deposited on a substrate. Epitaxial growth occurs in such a way that the crystallographic structure of the substrate is reproduced in the growing material, although the conductivity and the doping level of the epitaxial layer can be independent of the underlying substrate layer. Silicon substrates with epitaxial layers are commonly used in complementary metal-oxide silicon (CMOS) semiconductor devices, bi-CMOS devices, high-voltage devices, and bipolar devices.
FIGS. 4A, 4B and 4C show the alignment problems that can occur within a pattern in an epitaxial layer relative to the pattern of a substrate layer. In FIG. 4A, pattern shift has occurred. The pattern 406 in a substrate layer 402 has shifted to the right as the pattern 408 in the epitaxial, or epi layer 404. In FIG. 4B, pattern distortion has occurred. The pattern 436 in the substrate layer 432 has become distorted as the pattern 438 in the epi layer 434. That is, the pattern 438 is smaller in width than the pattern 436. In FIG. 4C, pattern washout has occurred. The pattern 466 in the substrate layer 462 has washed out as the pattern 468 in the epi layer 464. These types of alignment problems can occur because of non-ideal deposition of the epi layers, and/or because of other improper processing. The patterns of FIGS. 4A, 4B and 4C can be alignment marks, used for alignment in the subsequent processing of epi layers and other layers.
Once the alignment problems of FIGS. 4A, 4B and 4C occur, adjustments must be made to the position of the features on subsequent layers in order to compensate for the areas induced in the epi layer. Selecting the correct amount of adjustment, however, is usually complicated by the fact that the effects are dependent on such varying factors as substrate orientation, deposition rate, deposition temperature, and silicon source. Further, in the case of pattern washout of FIG. 4C in particular, subsequent processing performed relative to the epi layer 464 will likely fail, because the semiconductor processing equipment will most likely not be able to align with the washout pattern 468. This alignment failure may be corrected by manual alignment that is time intensive and costly.
The present invention provides an alternative method of forming an epi layer on a semiconductor wafer.